
PIC16F946
DS41265A-page 250
Preliminary
2005 Microchip Technology Inc.
TABLE 19-12: SPI MODE REQUIREMENTS
FIGURE 19-15:
I2C BUS START/STOP BITS TIMING
Param
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
70*
TSSL2SCH,
TSSL2SCL
SS
↓ to SCK↓ or SCK↑ input
TCY
——
ns
71*
TSCH
SCK input high time (Slave mode)
TCY + 20
—
ns
72*
TSCL
SCK input low time (Slave mode)
TCY + 20
—
ns
73*
TDIV2SCH,
TDIV2SCL
Setup time of SDI data input to SCK edge
100
—
ns
74*
TSCH2DIL,
TSCL2DIL
Hold time of SDI data input to SCK edge
100
—
ns
75*
TDOR
SDO data output rise time
3.0-5.5V
—
10
25
ns
2.0-5.5V
—
25
50
ns
76*
TDOF
SDO data output fall time
—
10
25
ns
77*
TSSH2DOZSS
↑ to SDO output high-impedance
10
—
50
ns
78*
TSCR
SCK output rise time
(Master mode)
3.0-5.5V
—
10
25
ns
2.0-5.5V
—
25
50
ns
79*
TSCF
SCK output fall time (Master mode)
—
10
25
ns
80*
TSCH2DOV,
TSCL2DOV
SDO data output valid after
SCK edge
3.0-5.5V
—
50
ns
2.0-5.5V
—
145
ns
81*
TDOV2SCH,
TDOV2SCL
SDO data output setup to SCK edge
TCY
——
ns
82*
TSSL2DOV
SDO data output valid after SS
↓ edge
—
50
ns
83*
TSCH2SSH,
TSCL2SSH
SS
↑ after SCK edge
1.5TCY + 40
—
ns
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
91
92
93
SCL
SDA
Start
Condition
Stop
Condition
90